Power integrity occurs at both the component level and the PCB level. As others have mentioned, power integrity issues can cause signal integrity issues (jitter, power/ground bounce, EMI). While most of the simpler power integrity guidelines focus only on the PCB level, the PCB and package must work together to provide a stable power supply to the interconnect.
This guide will provide PCB designers with a comprehensive conceptual view of power integrity. While designers often have no control over their packages, they can take steps to ensure that their PCBs and component packages work together to provide a stable power supply. We will outline key approaches to ensuring power integrity in these areas, covering everything from stack design to optimal capacitor selection.
What determines the power integrity of a PCB?
Power integrity is a concept in both AC and DC; in the case of DC, we are concerned with properly sizing the copper traces to ensure a low DC voltage drop. Suppose a PCB is designed without considering power integrity. In that case, the voltages observed on the power rails may be as shown below. During the phase of I/O switching, current pulses pulled from the PCB’s power supply network (PDN) can excite transients on the power bus. An example of a logic circuit repetitively switching is shown below.
The most common examples of this happening are high-speed components with very fast switching speeds; switching more I/O simultaneously results in greater power requirements, so more noise is likely on the power rails. When amplifying the transient response, the transient decays with several time constants, most notably a long, low-frequency time constant that generates the most noise on the power rails.
Typically, when the signal rise time is faster for a given PDN structure, the generated ripple may have greater overshoot or multiple time constants associated with higher-frequency underdamped oscillations. These oscillations are undesirable for two reasons:
- They appear as noise (both timing noise and signal level noise) on the output signal, which can lead to misinterpretation of logic levels.
- They generate radiated EMI that can be measured from the board, usually from the edges.
For these two reasons, the designer must ensure that the regulator’s DC voltage output is as stable as possible.
PDN Impedance, Inductance, and Capacitance
The impedance of the PDN in the PCB will be a major determinant of power integrity. Voltage regulators also play a role through feedback loops (see below), but designing for PDN impedance is a PCB designer’s job description. The goal is to minimize the PDN impedance as much as possible, typically below the 100 mOhm level.
Collectively, these elements will determine the impedance spectrum of the PDN. The various contributors to the PDN are shown in the figure below, and these contributions are delineated roughly by frequency range. The impedance spectrum shown here consists of many capacitors, typical of digital processors with high I/O counts running at fast edge rates.
PDN Topology
All PDNs powering advanced processors are multi-port networks. They require multiple stabilizing voltages, ranging from high values to low logic levels. On high-pin-count processors, it is common for the voltage to drop from higher logic levels (5V0 or 3V3) to as low as 0V8.
The power tree that defines the PDN for advanced processors is shown below. This example is intended to illustrate how to build the different power rails from the mains or regulators that power the entire system.
The above example is intended to generalize only some digital components. Still, it should illustrate that many components will have multiple power rails. A digital processor powered by the above power topology may be any type of component, such as a large FPGA, network processor, MPU, large MCU, GPU, or other specialized processor. The I/O on the processor draws power from the power rails so that these power rails may experience significant transient noise in the PDN.
The topology above should illustrate the need for two design requirements: isolation between the rails, especially two different rails supplied by the same regulator, so they do not pass noise between each other. Each rail must also have a low impedance value to ensure low noise excitation.
Printed Circuit Board Stacks and Materials
Regarding power integrity, choosing materials in the PCB stack is important in providing the capacitance needed to ensure a stable power supply. In addition, the layer arrangement should provide power rails to be placed adjacent to the grounding layer on the thin layer. This will help ensure that the stacked layers provide sufficient capacitance for signals with bandwidths up to approximately 1 GHz.
When the available capacitance in planar layers is insufficient and discrete capacitors are limited by parasitic effects, the required capacitance can be provided by embedded capacitive materials (ECM). These are very thin films (some less than 1 mil thick) with high Dk values up to 30. These materials may also have very high losses that will absorb EMI propagating through the PCB substrate, thereby reducing EMI radiated from the board edge.
In terms of PDN impedance, the impact of these materials falls into four parts:
- Reducing impedance by providing higher capacitance at mid-range frequencies (up to 1 GHz)
- Shifting the PDN resonance associated with the power/grounding layer pair to lower frequencies
- Suppresses PDN resonance peaks in the GHz range associated with power/ground layer pairs
- Move PDN impedance valleys (from 0.1 to 1 GHz) associated with planar capacitance to lower frequencies.
The effect of these materials is shown below. As the dielectric thickness decreases, we can see that the resonance peaks in the PDN decay and move to lower frequencies. Similar results can be seen if we increase the dielectric loss in the material.
Package Parasitic Effects
Component packages have parasitic effects related to the package structure, and the component package has its own PDN impedance. The package impedance is combined with the PCB impedance, and together, they determine the amount of noise at the power inputs of the logic circuits on a semiconductor chip. Modern processors include in-package capacitors to help suppress transient excitation and extend useful signal bandwidth into the GHz range.
More than PCBs and Packaging
We covered everything about PCBs and packaging, including some of the most complex design features and models in advanced packaging.PCB designers control board layout, stacking, placement/routing, and packaging. In terms of power regulation strategies, we have not yet covered two important topics:
- Voltage regulator modules (VRMs) for large, high-speed processors
- Simulation in schematics and PCB layout
VRM Modules
The structure of the PDN and the fact that many advanced components require multiple power rails require multiple regulator modules that are parallel branches of each other. The role of the fixed supply regulator is to compensate for the voltage drop and maintain the target output voltage through a feedback loop (the FB pin on most regulators). The feedback loop must respond fast enough and modulate the output to stabilize the output voltage. Factors affecting the response of a regulator’s feedback loop occur at the layout and component levels.
In addition to VRM design and layout, designers should also focus on designing the correct stack and capacitor/material selection to ensure a sufficiently low PDN impedance over its operating bandwidth. As discussed above, layout and placement can also affect power integrity by creating parasitic effects.
Simulation
Simulations can be performed in AC or DC, as well as in schematics or completed PCB layouts. AC power integrity simulations are most important for high-speed PCBs operating at signal bandwidths up to GHz because they can reveal the power bus ripple when I/Os starts switching.
The AC simulations in the schematic are SPICE-based simulations that allow checking the stability of the capacitor network used for decoupling/bypassing. These models allow for estimating the power bus response and assessing the capacitors’ adequacy in the PDN. It is also necessary to assess the isolation between different power rails powered by the same regulator, or VRM, which can be determined by evaluating the transfer impedance.
AC simulations can also be performed in a PCB layout, but this requires an EMF solver to predict the behavior of the signal in space and time for a given PDN structure in the PCB. These simulations are computationally intensive and require specialized software.
Despite the importance of AC simulation in advanced products, DC simulation still has a place in high-speed PCBs. The large amount of I/O switched in these PCBs’ main processor creates a demand for several amps. When you use a large high-speed board that serves multiple peripherals, such as a backplane, you must support about 100 A of current throughout the system, including the power rails that power the I/O on the fast processors. Therefore, it is important to identify and eliminate extreme currents in the power rails.
Reference:
The Beginner’s Guide to PCB Power Integrity: From Board to Package, by Zachariah Peterson
